Prior programmable memories have been implemented using split-gate non-volatile memory (NVM) cells. These programmable memories can be implemented as stand-alone memory integrated circuits or can be embedded within other integrated circuits, as desired.
FIG. 1 (Prior Art) is an embodiment 100 for a split-gate memory cell having metal silicide regions. A control gate (CG) 112 and a select gate (SG) 110 are formed over a substrate 102. A source region 108 and a drain region 104 are formed within substrate 102. An oxide dielectric layer 130 is formed above substrate 102 below the select gate (SG) 110. The charge storage layer 132 is positioned below the control gate (CG) 112 and is positioned between the control gate (CG) 112 and the select gate (SG) 110. The charge storage layer 132 can be a discrete charge storage layer, if desired, such as a nanocrystal discrete charge storage layer. The charge storage layer can also be a continuous charge storage layer, if desired, such as a polysilicon floating gate charge storage layer. An anti-reflective dielectric layer 128 is positioned above the select gate (SG) 110 and below the charge storage layer 132. Spacers 114, 116 and 118 are also depicted. These spacers can be implemented as nitride spacers, a combination of nitride and oxide spacers, or as spacers from other material, as desired. Spacer 114 is located adjacent the select gate (SG) 110. Spacer 116 is located above the select gate (SG) 110 and adjacent the control gate (CG) 112. And spacer 118 is located adjacent the control gate (CG) 112. Regions 120, 122, 124, and 126 are metal silicide regions that are formed within drain region 104, select gate (SG) 110, control gate (CG) 112, and source region 108, respectively.